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Part 1 ― Update on the Innovative EXREAL Platform^(TM)


Versatile platform and its derivatives assemble and focus diverse technology resources to boost microcomputer chip and embedded system development

The Renesas EXREAL Platform^(TM), first announced in 2006, is continuously being enhanced and used to great advantage for our R&D activities, providing a boost for the implementation of advanced technology in new microcomputers and other LSI devices. Versatile, highly capable, and incorporating diverse resources, it serves as a mother platform for system-on-chip (SoC) development projects. The platform is the foundation for research underway at numerous universities and research institutions into chip miniaturization, multi-core designs, and techniques for saving power, among other things. It has served with distinction as a key tool in the development of new Renesas processors, as exemplified by the project that created the MX massively parallel processor, which uses a matrix architecture to excel at image processing. This article examines how the EXREAL Platform^(TM) and application-specific versions of it continue to advance and grow with new technology to accelerate microcomputer chip and embedded system development. Significantly, some of the technologies the latest version platform applies were developed using previous versions.

Addressing customer demands for the rapid development of chips with wider spans of sophisticated functions

Renesas has accumulated extensive experience in the two years since we began applying our EXREAL Platform^(TM) mother platform to assemble and focus diverse technology resources for accelerating the development of SoC (System on Chip) devices. The platform has proven to be highly successful for the design of devices optimized for applications such as mobile phones and digital AV equipment. It implements a forward-looking chip development approach that has met the needs of customers requiring short design cycles for SoCs that deliver larger sets of sophisticated functions. For example, versions of the EXREAL Platform^(TM) optimized for particular applications have been used by Renesas to produce advanced products such as SH-Mobile SoCs for mobile phones and SH-Navi devices for car navigation systems.

Recent Renesas R&D programs have resulted in several evolutions of the EXREAL Platform^(TM). Two of these are new versions of the platform: the EXREAL-Media for the rapid design of multimedia products, and the MCU Development Platform for the development of new microcomputers. Another evolution is the incorporation of key leading-edge technologies into the EXREAL Platform^(TM), especially multiple parallel-processing CPU cores and methods for lowering SoC power consumption.

Accommodating market trends of divergence and convergence

The development and application of our EXREAL Platform^(TM) is being driven by a major global market trend in electronics: the adoption of digital technology in an expanding range of products. This trend is creating demand for both 'divergence' and 'convergence'. On one hand, mobile phones now offer many more functions than just voice capability (divergence), as evidenced by popular devices that can be used as e-mail terminals, music players, and receivers for terrestrial digital TV broadcasts. On the other hand, there is increasing standardization of functions such as video playback and network connectivity across different applications (convergence).

For efficient system development, divergence and convergence have made it essential for R&D teams to use a 'mother platform' to develop additional platforms adjusted for different applications. However, for many companies the increasing complexity of systems makes it impractical to develop such platforms from scratch, as was common practice in the past. The result is a growing engineering need for development platforms that allow common functions (intellectual property [IP]) like graphics, video, audio, security (encryption), and networking to be shared across different applications, including mobile phones, car navigation, and digital AV equipment.

Multiple benefits derive ― lower cost, improved reliability, shorter design cycles, etc. ― if product development groups can adopt a platform and tailor it for particular purposes, while still being able to share IP across different application fields. The Renesas EXREAL Platform^(TM) fits well with this engineering approach. Its ongoing evolution (see Figure 1) is a successful practical realization of the platform concept that is expanding in complexity and capability. It's becoming an increasingly important R&D tool both internally by our development groups and externally by many of our customers' engineering teams.

Related article in EDGE back issue: Vol.12

Figure 1: EXREAL Platform^(TM) concept.
The platform consists of the individual components and the interconnection technology that links them together. The aim is to improve reliability, efficiency, and agility. The concept allows new technologies to be put to immediate use and also enables HW and SW IP from various products to be reused across different applications.
Sharing IP across different applications

A key reason for the utility and flexibility of the EXREAL Platform^(TM) is its ability to create optimum system architectures: The platform accomplishes this because it uses three types of interconnection technology to integrate various components of end products:

  • Hardware (HW) interconnection technology links different hardware elements, including multiple CPU cores
  • Software (SW) interconnection technology links different software applications, including multiple operating systems
  • Technology for testing and verifying these interconnections helps engineers optimize system designs by ensuring the tight interoperation of hardware and software.
  • Diverse resources can be linked by these interconnection technologies. We call the hardware elements and software applications 'component technologies' to indicate their enhanced level of reusability. In managing them, our overall goal is to increase the reusability of IP, and there are three primary objectives:

  • To enhance the individual CPUs, IP, and other resources
  • To make processes more independent, thereby improving interconnection flexibility
  • To incorporate user and third-party hardware and software IP, as well as our own IP products. (Examples of IP include CPUs, image decoders, memory interfaces, drivers, operating systems, middleware, and applications.)
  • COMPONENT TECHNOLOGIES

    Because the EXREAL Platform^(TM) makes various IP products separately selectable components and allows component technologies to be mixed and matched in numerous ways, engineers can quickly configure versions of the platform to fulfill diverse sets of product requirements. The use of proven components in those application-specific platforms improves design agility, increases engineering efficiency, shrinks the design and debug process, and helps boost end-product reliability.

    Implementing enhanced multimedia capabilities

    As previously mentioned, Renesas has successfully used application-specific platforms derived from the EXREAL Platform^(TM) to develop SoCs such as the SH-Mobile G series for mobile phones and the SH-Navi series for car navigation systems. Divergence and convergence are very evident in these market segments and in others such as digital home appliances. The TV broadcast reception (one-segment type), high-quality video recording, and high-fidelity audio functions typically incorporated into such end products are all derived from basic capabilities of audio-visual (AV) equipment. Simultaneously, encryption, networking, and communication functions such as Ethernet connectivity are starting to appear in AV equipment.

    To facilitate progress in this broad market area, we recently created the EXREAL-Media platform, which supports the varied requirements of current and future multimedia applications (see Figure 2). This version of the EXREAL Platform^(TM) has proven to be very effective in development projects for HDD and DVD recorders, digital TVs, digital still cameras, digital video cameras, and car navigation systems. The EXREAL-Media platform application-specific platform provides functions common to all of these products: video and audio processing, display control, encryption, graphics, and networking (see Figure 3).

    Figure 2: Roadmap for application-specific platforms produced from the EXREAL Platform^(TM).
    Phase 3 includes the EXREAL-Media and the MCU Development Platform.

    Figure 3: Examples of 'divergence' from the EXREAL-Media platform to different applications.
    Aiding the design of multi-core SoCs

    The latest trends in component and interconnection technologies are accommodated by and utilized in the EXREAL Platform^(TM). For example, it's not unusual today for an SoC device to be the key semiconductor device in electronic products that have high levels of integration. Indeed, the chip can be critical to a product's competitiveness. Yet, due to power consumption issues, there are limits to the performance obtainable form single-core SoCs. The result is the growing application of multi-core technology, which Renesas is already using in our SH-Mobile G series and other SoCs that have been developed or and are now in development using the EXREAL Platform^(TM).

    As we rapidly build our experience in multi-core systems, we are moving beyond the heterogeneous, AMP (Asymmetric Multi Processing), and SMP (Symmetric Multi Processing) system architectures previously used. Currently we are working on a new heterogeneous chip design that combines all three of these architectures in the same chip (see Figure 4).

    Rather than just targeting higher performance, Renesas' basic stance is to work also on reducing the power consumption of the individual cores with the aim of achieving greater energy efficiency when the devices are used in consumer products. For example, recent R&D projects have produced advanced methods for reducing the power consumption of multi-core SoCs. These approaches are being or will be applied in the EXREAL Platform^(TM) and its application-specific derivatives. Two of them are described in other stories in this issue: partial clock activation and an LSI with eight CPU cores .

    Figure 4: Concept for the next generation of embedded multi-core technology.
    Renesas is working on a 'New Heterogeneous' system architecture that combines heterogeneous, AMP, and SMP types.
    Taking advantage of the massively parallel processor's 1024 CPUs

    Another technology achievement that Renesas plans to apply to the EXREAL Platform^(TM) and its derivatives is the massively parallel processor with a matrix architecture we have developed. (This device is abbreviated below as the 'MX' processor). It operates 1024 ultra-small processor in parallel to perform high-speed signal processing for AV equipment applications. Thus it will greatly expand the capabilities of the EXREAL-Media platform. Having power consumption low enough for use in portable devices, the MX processor delivers signal processing performance surpassing high-end DSPs and rivaling that of hardware accelerators (see Figure 5).

    In brief, the MX is a massively parallel SIMD (Single Instruction Multiple Data) processor optimized for multimedia processing. The 1024 ultra-small processors have closely coupled SRAM, and the chip uses a sub-CPU for control. To perform an operation, 1024 32-bit data values are first loaded into the SRAM, then a bit-slice operation is performed whereby the lower 2 bits of each of the 1024 data values are read simultaneously and operated on in parallel by the 1024 processing units. This operation repeats until the most significant bits are reached. The result is that the 1024 data values are processed in only 16 cycles (see Figure 6).

    A feature of the processor is its level of functional integration and ease of modification. By optimizing the architecture for highly parallel algorithms, redundancy is reduced and the hardware can be made smaller. Our R&D on an application development environment for the MX has produced the MX Debugger, MX Simulator, MXGEN development tools, and an MX evaluation board.

    The MX Debugger works by adding "MX windows" for MX debugging to the CPU debugger used on the SoC into which the MX is integrated (see Figure 7). These are used like standard debugging windows and include memory, register, program, and profile displays. They allow the internal state of the CPU and MX to be monitored during stepwise execution of application code. The MX Simulator is a debugger that can be used on a PC without the need for target hardware. For ease of use, it has the same interface as the MX Debugger. The MXGEN tools enable syntax checking, optimizing software execution speed, and similar engineering tasks.

    Related article in EDGE back issue: Vol.13

    Figure 5: Characteristics of the MX implementation.
    The chip's high level of functional integration (1024 CPUs) and ease of modification make it suitable for use in SoCs.

    Figure 6: Structure of the massively parallel processor with a matrix architecture (MX).

    Figure 7: MX debugger solution.
    The MX windows are integrated into the debugger for the internal CPU.
    INTERCONNECTION TECHNOLOGIES

    The EXREAL Platform^(TM) provides many hardware interconnection technologies. They are used for linking the CPU, multi-core IP, and various other hardware IP for functions such as the VPU (Video Processing Unit), 3D graphics accelerator, DDR SRAM interface, USB 2.0 interface, and authentication and encryption functions. An IP wrapper is used to incorporate Renesas and certified third-party IP cores into the platform's HW interconnection system.

    Establishing real-time, scalable connections between IP cores

    There are three main parts to the platform's HW interconnection technology: a scalable on-chip bus, power interconnections, and security interconnections. The on-chip bus links together the various hardware IP elements so that real-time and scalable connections can be established between the IP cores. The bus can be configured to accommodate requirements such as transmission speed and number of IP modules being connected.

    The power interconnection technology performs efficient power management. It uses a resource manager and power-control function to reduce power consumption. The security interconnection technology has an access-control function that manages access between IP modules to boost system reliability.

    Allowing one software application to call another

    The platform's SW interconnection technology provides software interoperation, whereby one software application can call another. Key features are multi-level APIs, a performance scheduler, and a distributed object framework. The multi-level APIs provide seamless integration between hardware and software. They are designed to encourage reuse of software resources using wrappers and standardization, and they enable the implementation of separate multi-level APIs for each type of application. The technology ensures that software at the driver, operating systems (including multiple OSs), middleware, application, and other levels can work together.

    Three levels of API are defined to link between the different software levels. One is the API between the application and middleware: the application-level API. Another is the API between the middleware and OS: the middleware-level API. The third is the API between the OS and drivers: the device-level API. This multi-tiered structure restricts system customization to the application level only, while still allowing modifications to the middleware.

    Wrappers handle differences between the various standard APIs and operating systems used in different product categories. The performance scheduler provided by the SW interconnection technology controls parameters such as the operating frequency and clock, as well as tasks such as turning the power supply on or off. The scheduler is used in conjunction with the compiler, user programs, and other software to reduce power consumption.

    Using domain separation and domain interoperation to improve reliability

    Renesas has also developed technologies to improve the reliability of multi-core SoC chips: the EXREAL-ExARIA domain interoperation technology and the EXREAL-ExVisor domain separation technology (see Figure 8). Both are integrated into SoCs as part of the EXREAL Platform^(TM) to enable quick development and integrated management for that use multiple CPUs.

    Domain interoperation is a technology for communicating between multiple operating systems. It provides a common API that can be used on existing OSs without having to modify the OS, regardless of whether that OS is control or data processing oriented. Not only can this technology be used for OSs of the same type, it can also be used for communication between different types of OS. This makes it possible to configure multi-core system quickly without any loss of compatibility caused by system expansion.

    Domain separation is a technology for preventing conflicts between separate OSs. It detects and prevents interference with hardware IP such as memory areas with high security or reliability requirements. Detection uses a hardware-level resource protection function that prevents software from accessing other domains. The technology can be used on existing OSs without requiring any modifications to the OS. On the SH-4A multi-core system, the function is implemented in hardware.

    Figure 8: Domain interoperation using EXREAL-ExARIA and domain separation using EXREAL-ExVisor on a multi-core system.
    Reliability is improved by allowing a clear identification of which elements in each domain can interoperate and which remain separate.
    TESTING AND VERIFICATION TECHNOLOGY

    The testing and verification technology used in the EXREAL Platform^(TM) and its variants supports a tightly optimized 'interlinking' of hardware and software. Because the platform tests hardware and software together, engineers can estimate in advance the requirements for parameters such as operating performance and power consumption. This saves time by helping to prevent unnecessary development rework.

    Offering function-model libraries that simplify test configuration

    The EXREAL Platform^(TM) provides a System-C-based performance evaluation system. Engineers configure tests by selecting required items from various resources:

  • Function-model libraries for processors, buses, peripheral IP cores and other on-chip resources
  • Libraries of routines for analyzing performance and power supply operation
  • User-defined models; and drivers, middleware, and application code
  • Other software and hardware IP.
  • Results from systems tests can be generated in various forms. Examples include profile data such as the power supplied to each IP, power supply output in each mode of operation, and power supply load versus time.

    Allowing hardware changes without software modifications

    In the process of using the EXREAL Platform^(TM) to develop and test an SoC device or other type of system, the engineering team can implement different solutions as necessary to strike an optimum balance between software and hardware. This is especially beneficial for the development of large-scale systems.

    After development is complete, another important benefit arises: the engineers can change the hardware configuration easily without having to modify the system's software resources. That is, they can construct a system in which the 'software can operate without concern for the hardware' (see Figure 9).

    An important aspect in making the software independent of the hardware is that the roles of the platform's various software APIs are defined in three levels, as described previously and shown in Figure 9. Users perform application development at a level above these layers. Because changes to low-level IP do not influence the higher levels, the system development team can choose between different implementations of the same API.

    Significantly, splitting the APIs into these different levels also makes it easier to differentiate products into low-end, standard, mid-range, and top-end models, as Figure 9 also shows. With the multi-level API approach. Engineers can achieve combinations of power consumption, performance, and functionality by carefully selecting hardware that excels at particular algorithms. This type of optimization would not be possible using a general-purpose microcontroller.

    Looking into the future, Renesas plans to offer additional optimized versions of the EXREAL Platform^(TM). We aim to provide significant improvements in the efficiency of new product development, while also helping customer to implement product range expansion (horizontal development). We also plan to continue enhancing and adding to the component and interconnection technologies used in the platform. Simultaneously, we will make full use of the advanced technologies emerging from the EXREAL Platform^(TM) in the development of our general-purpose microcomputers. The previously mentioned MCU Development Platform version is being used for this purpose (see Figure 10). It illustrates the some of the most important overall benefits of the platform concept.

    Figure 9: Example of API interoperation using SW interconnection technology.
    Changes to the low-level IP have no effect on the upper levels. Also, different implementations of the same API can be selected.

    Figure 10: The MCU Development Platform.
    This chip-development tool was produced to apply the EXREAL Platform^(TM) concept to the design of new Renesas microcomputers. Devices in the RX family are the first to benefit from this approach.
    Applying the MCU Development Platform to create the RX family

    The MCU Development Platform was a major advantage for the Renesas R&D team that developed our new RX family of microcomputers. The platform's capabilities facilitated the work of merging our existing M16C, H8S, R32C, and H8SX families of 16 and 32-bit CISC MCUs into a single architecture. Devices in the new product line are next-generation microcomputers with a particular focus on maintaining continuity with the characteristics and the peripheral functions and other IP of previous-generation chips. This continuity will help preserve customers' system engineering investments.

    Aided by the features and capabilities of the EXREAL Platform^(TM) that can be applied in microcomputer development, Renesas engineers will be able to reuse IP from existing devices across its product range, while reducing the design workload by 30% and shortening chip development times by an average of four months. These advantages will let us deliver advanced chips to customers in a timely manner so they can capitalize on emerging market opportunities.

    The other six stories in this Special Feature section cover technologies that Renesas has announced at prestigious conferences such as the 2007 Symposium on VLSI Circuits, 2007 International Electron Devices Meeting (IEDM), and 2008 International Solid-State Circuits Conference (ISSCC). Some of these technologies apply to the EXREAL Platform^(TM).

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