Technology to Reduce Leak Current in High-performance CMOS Produced by a 45nm Process
2007 IEDM Paper No.6.4 describes a method for silicon ion implantation that significantly alleviates the problem of increased leak current in high-speed CMOS that uses nickel silicide
|Presented by: Renesas Technology Corporation|
Traditional methods for using nickel silicide technology for controlling wafer crystal orientation to increase the operating speed of CMOS in 45nm and finer processes are problematic. They result in a severe increase in n-channel MOSFET leak current. To counter this problem, a Renesas R&D team has developed a technique that uses silicon ion implantation. The engineers validated their new approach on a prototype inverter circuit, obtaining a reduction in leak current and achieving good circuit operating characteristics.
|Improving CMOS performance by controlling wafer-crystal orientation|
Semiconductor devices have traditionally used silicon wafers with a crystal orientation called "Si (100)" (referred to below as "<100> wafers"). When CMOS circuits are fabricated on these wafers, the performance of p-channel MOSFETS is significantly worse than that of n-channel MOSFETs. However, if silicon wafers with the "Si (110)" crystal orientation (referred to below as "<110>" wafers) are used, the performance of p-channel MOSFETs improves to the point that it is considerably better than on <100> wafers. This has led to considerable research into the use of <110> wafers for high-speed CMOS.
Another trend in semiconductor process technology is the use of nickel silicide, which is becoming a standard technique in 65nm and finer CMOS processes. A silicide is an alloy of silicon and high-melting-point metals, and its low resistivity has the advantage of reducing the increase in resistance associated with greater levels of miniaturization. Unfortunately, when a nickel silicide process was trialed with <110> wafers, the research results showed that this process increased the leak current in n-channel MOSFETs significantly. In seeking to identify the reason for this phenomenon, "we discovered that the increase in leak current was influenced by the channel orientation" explained Mr. Yamaguchi.
Figure 1 shows the case when channels with <110> and <100> orientations were formed on a <110> wafer. In the channel with <110> orientation, the influence of silicide increased the leak current by five orders of magnitude. For the <100> orientation, this increase was only two orders of magnitude.
To investigate the cause of the leak current, the MOSFET was placed in an electron microscope to observe the leak current path. As can be seen in Figure 2, the results showed abnormal nickel silicide growth in the <110> direction. For the <110> channel, the nickel silicide grows towards the channel area, causing the leak current to flow between the drain and source. For the <100> channel, however, the nickel silicide grows in the body (substrate) direction, creating a leak current path from the drain to the substrate.
|Using ion implantation to turn the crystal amorphous|
Armed with the knowledge that the nickel silicide growth was dependent on the crystal orientation, the Renesas researchers tried implanting silicon ions in the channel area. "We realized that the nickel silicide have more difficulty growing if the crystal orientation information could be eliminated," Mr. Kashihara said. Prior to the silicide forming process, silicon ions were implanted in the channel area to make the silicon crystal amorphous; that is, to make the structure of the material non-crystalline.
The results of this technology innovation were very positive. The leak current was reduced by five orders of magnitude for the <110> channel and two orders of magnitude for the <100> channel (see Figure 3). The newly developed process was then used to produce an inverter circuit built in 65nm CMOS. The prototype circuit had excellent operating characteristics (see Figure 4). The next step in this ongoing R&D program is to apply the new process technology to the development of high-speed CMOS using nickel silicide on a 45nm process.