H8S/2602

Product Specifications

Item

Specification

Packages:

CPU:

Upwards-compatibility with H8/300 CPU as well as H8/300H CPU
- Execution of H8/300 and H8/300H CPU object programs possible
General purpose register: 16-bit x 16
- Can also be used as 8-bit x 16, 32-bit x 8
Basic instructions: 69 types
- 8/16/32-bit operation instructions
- Multiplication/division instructions
- Powerful bit operation instructions
- Multiply-accumulate instructions
Addressing modes: 8 types
- Register direct （Rn）
- Register indirect （@ERn）
- Register indirect with displacement （@(d:16、ERn)/@(d:32、ERn)）
- Register indirect with post-increment/pre-decrement （@ERn+/@-ERn）
- Absolute address （@aa:8/@aa:16/@aa:24/@aa:32）
- Immediate （#xx:8/#xx:16/#xx:32）
- Program counter relative （@(d:8、PC)/@(d:16、PC)）
- Memory indirect （@@aa:8）
Address space: 16MB
- Program: 16MB
- Data: 16MB
High-speed operation
- All frequent instructions executed in 1-2 states
- 8/16/32-bit inter-register addition and subtraction: 1 state
- 8×8-bit inter-register multiplication: 3 states
- 16÷8-bit inter-register division: 12 states
- 16×16-bit inter-register multiplication: 4 states
- 32÷16-bit inter-register division: 20 states
CPU operating mode
- Advanced mode
Low power consumption states
- Switching to low power consumption state by SLEEP instruction
- CPU operating clock selectable

Clock oscillator:

Low power consumption states:

Operating mode:

Interrupt controllers:

2 types of interrupt control modes
- 2 types of interrupt control modes supported by INTM1 and INTM0 bit in system control register (SYSCR).
Priority level may be set using ICR
- Interrupt control register (ICR) can set 8 priority levels by module for interrupt requests other than NMI. NMI is always received as top priority (level 8) interrupt request.
Independent vector address
- Since independent vector addresses are allocated to all interrupt causes, cause distinction by interrupt processing routines is unnecessary.
7-pin external interrupt terminal
- NMI is always received as top-priority interrupt. Rising edge or falling edge selectable for NMI. ~IRQ5-~IRQ0 can select independently from falling edge, rising edge, dual-edge and level sense.
DTC control
- DTC can be initiated by interrupt demands.

Memory:

PC break controller
（PBC） :

Channels: 2ch （channel A, B）
Break address: 24-bit
- Can be masked by section
Compare conditions: 4 types
- Instruction fetch
- Data read
- Data write
- Data read/write
Target bus master
- CPU, CPU/DTC selectable
PC break exception processing executed as below following establishment of break conditions
- Immediately prior to execution of instruction fetched from set address (instruction fetch)
- Immediately after execution of set address data access instruction (data acess)
Module stop mode setting available

Data transfer controller （DTC） :

Arbitrary channel numbers transferrable
Transfer modes: 3 types
- Normal mode, repeat mode, block transfer mode
Continuous transfer of multiple data by a single initiating factor possible (chain transfer)
Direct designation of 16MB address spaces possible
Initiation by software possible
Setting of transfer units to bytes/words possible
Request to CPU by DTC-initiated interrupt possible
Module stop mode setting possible

I/O ports :

16-bit timer pulse unit
（TPU） :

Maximum 16 pulse I/O ports available
8 types of counter input clocks selectable for each channel
Following operation settings available for each channel
- Waveform output by compare match, input capture function, counter clear operation, simultaneous write to multiple timer counters (TCNT), simultaneous clear by compare match/input capture, register synchronous input/output through synchronous operation of counter, maximum of 15-phase PWM output through combination of synchronous operations
Channels 0 and 3 can set buffer operation
Channels 1, 2, 4 and 5 can each independantly set phase count mode
Cascade connection operation
High-speed access by 16-bit internal bus
26 types of interrupt causes
Automatic transfer of register data possible
Programmable pulse generator （PPG） output trigger generation possible
A/D converter conversion start trigger generation possible
Module stop mode setting available

Programmable pulse generator（PPG） :

Watchdog timer（WDT） :

Serial communication interface（SCI) :

Serial data communication format may be set to start-stop synchronous mode or clock synchronous mode
All duplex communications possible
- Independent transmit and receive portions enable simultaneous transmit/receive. Additionally continuous transmit/receive enabled by double buffer structure of both transmit and receive portions.
Arbitrary bit rate selectable by on-chip baud rate generator
- External clock selectable as transmit/receive clock source (SmartCard interface excluded).
LSB first/MSB first selectable (start-stop synchronous mode 7-bit data excluded)
Interrupt causes: 4 types
- Transmit end, transmit data empty, receive data full, receive error. Also, DTC initiation by transmit data empty or receive data full interrupt cause possible.
Module stop mode setting possible

【Start-stop synchronous mode】
- Data length: 7-bit/8-bit selectable
- Stop bit length: 1-bit/2-bit selectable
- Parity: Even parity/odd parity/no parity selectable
- Receive error detection: parity error, overrun error, framing error
- Break detection: Break detection possible by direct read of RxD terminal level when framing error generated.
【Clock synchronous mode】
- Data length: 8-bit
- Receive error detection: overrun error
【SmartCard interface】
- Automatic error signal sending when parity error detected during receive
- Automatic resending of data when error signal received during transmit
- Direct convention/inverse convention both supported

A/D converter :

Resolution: 10-bit
Input channels: 12ch
Conversion time: 13.3μs per channel （at 20MHz operation）
Operating modes: 2 types
- Single mode: 1 channel of A/D conversion
- Scan mode: 1-4 channels of continuous A/D conversion
Data registers: 8
- A/D conversion results held in 16-bit data registers corresponding to each channel
Sample & hold functions included
A/D conversion start methods: 3 types
- Software
- 16-bit timer pulse unit (TPU) conversion start trigger
- External trigger signal
Interrupt causes
- A/D conversion finish interrupt request （ADI） generation
Module stop mode setting possible