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Product Specifications

Item Specification
  • High-speed H8S/2600 central processing unit with an internal 16-bit architecture
    • Upward-compatible with H8/300 and H8/300H CPUs on an object level
    • Sixteen 16-bit general registers
    • 69-basic instructions
Memory Map:
  • On-chip memory
    ROM Type Model ROM RAM Remarks
    F-ZTAT Version HD64F2628 128 kbytes 8 kbytes Under development
    Masked ROM Version HD6432628 128 kbytes 8 kbytes Under development
    HD6432627 128 kbytes 6 kbytes Under development
PC Break Controller (PBC):
  • The PC break controller (PBC) provides functions that simplify program debugging. Using these functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-circuit emulator.
Bus Controller (BSC):
  • The H8S/2600 CPU is driven by a system clock, denoted by the symbol f.
  • The bus controller controls a memory cycle and a bus cycle. Different methods are used to access on-chip memory and on-chip support modules. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU and data transfer controller (DTC).
Data Transfer Controller (DTC):
  • This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data.
  • The DTC's register information is stored in the on-chip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information.
I/O Ports:
  • General I/O ports
    • I/O pins: 59
    • Input-only pins: 17
16-Bit Timer Pulse Unit (TPU):
  • This LSI has an on-chip 16-bit timer pulse unit (TPU) comprised of six 16-bit timer channels.
8-Bit Timers (TMR):
  • This LSI has an on-chip 8-bit timer module with four channels operating on the basis of an 8-bit counter.
  • The 8-bit timer module can be used to count external events and be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers.
Programmable Pulse Generator (PPG):
  • The programmable pulse generator provides pulse outputs using the 16-bit timer pulse unit (TPU) as a time base.
Watchdog Timer(WDT):
  • The watchdog timer (WDT) is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow.
  • When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows.
Serial Communication Interface (SCI):
  • This LSI has two independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). The SCI also supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function.
Hitachi Controller Area Network (HCAN):
  • The HCAN is a module for controlling a controller area network (CAN) for realtime communication in vehicular and industrial equipment systems, etc. For details on CAN specification, refer to Bosch CAN Specification Version 2.0 1991, Robert Bosch GmbH.
Synchronous Serial Communication Unit (SSU):
  • This LSI has two independent synchronous serial communication unit (SSU) channels. The SSU has master mode in which this LSI outputs clocks as a master device for synchronous serial communication and slave mode in which clocks are input from an external device for synchronous serial communication. Synchronous serial communication can be performed with devices having different clock polarity and clock phase. In addition, synchronous serial communication can also be performed between multiple processors (multi-processor communication).
A/D Converter:
  • This LSI includes a successive approximation type 10-bit A/D converter that allows up to sixteen analog input channels to be selected.
Clock Pulse Generator:
  • This LSI has an on-chip clock pulse generator that generates the system clock (ø), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator, PLL circuit, clock selection circuit, medium-speed clock divider, and bus master clock selection circuit.
Power-Down Modes:
  • Supports various power-down states
  • Compact package
    Package (Code) Body Size Pin Pitch
    QFP-100 FP-100M 14.0 × 14.0 mm 0.5 mm

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