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V850E/IF3, V850E/IG3

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Product Overview:

The V850E/IF3 and V850E/IG3 are 32-bit single-chip microcontrollers that use the V850E1 CPU core and incorporate ROM/RAM and various peripheral functions such as DMA controller, timer/counter, watchdog timer, serial interfaces, A/D converter, and on-chip debug function and enable an extremely high cost-performance for applications such as motor inverter control.

Pin Count / Memory Size Lineup:

map_v850eix3

Key Features:

Operation supply voltage:

  • VDD = EVDD = 3.5 to 5.5 V / AVDD0, AVDD1 = 4.5 to 5.5 V
  • VDD0 = VDD1 = EVDD0 = EVDD1 = AVDD0 = AVDD1 = AVDD2 = 4.0 to 5.5 V (when A/D converter 0, 1 or 2 is operating)
  • VDD0 = VDD1 = EVDD0 = EVDD1 = AVDD0 = AVDD1 = AVDD2 = 3.5 to 5.5 V (when none of A/D converters 0 to 2 is operating)

Max. frequency: 64 MHz
ROM capacities: 128 KB to 256 KB
RAM capacities: 8 KB to 12 KB
Package: 80-pin plastic LQFP package and 100-pin plastic LQFP , 161-pin plastic FBGA package
Minimum instruction execution time: 15.6 ns (at internal 64 MHz operation)
General-purpose registers: 32 bits x 32
CPU features:

  • Signed multiplication (16 bits x 16 bits -> 32 bits or 32 bits x 32 bits -> 64 bits): 1 to 2 clocks
  • Saturated operation instructions (with overflow/underflow detection function)
  • 32-bit shift instructions: 1 clock
  • Bit manipulation instructions
  • Load/store instructions with long/short format
  • Signed load instructions

Interrupts/exceptions:

  • Non-maskable interrupts: 1 source (external: none, internal: 1)
  • Maskable interrupts: 88 sources (external: 15, internal: 73) / 95 sources (external: 21, internal: 74)
  • Software exceptions: 32 sources
  • Exception traps: 2 sources

DMA controller: 4 channels

  • Transfer unit: 8 bits/16 bits
  • Maximum transfer count: 65536
  • Transfer type: 2-cycle
  • Transfer modes: Single/single step/block
  • Transfer targets: On-chip peripheral I/O <-> Internal RAM
  • On-chip peripheral I/O <-> On-chip peripheral I/O
  • Transfer request: On-chip peripheral I/O/software
  • Next address setting function

I/O lines: Total: 48 (Input ports: 4, I/O ports: 44) / 64 (Input ports: 8, I/O ports: 56)
Timer/counter function:

  • 16-bit interval timer M (TMM): 4 channels
  • 16-bit timer/event counter AA (TAA): 5 channels
  • 16-bit timer/event counter AB (TAB): 2 channels
  • 16-bit timer/event counter T (TMT): 2 channels
  • Motor control function (uses timer TAB: 2 channels (TAB0, TAB1), TAA: 2 channels (TAA0, TAA1))
  • 16-bit accuracy 6-phase PWM function with deadtime: 2 channels
  • High-impedance output control function
  • A/D trigger generation by timer tuning operation function
  • Arbitrary cycle setting function
  • Arbitrary deadtime setting function
  • Watchdog timer: 1 channel

Serial interfaces:

  • Asynchronous serial interface A (UARTA)
  • Asynchronous serial interface B (UARTB)
  • Clocked serial interface B (CSIB)
  • I2C bus interface (I2C)
  • UARTA0/CSIB0: 1 channel
  • UARTA1/I2C: 1 channel
  • UARTA2/CSIB1: 1 channel
  • UARTB/CSIB2: 1 channel

A/D converter:

  • 12-bit resolution A/D converters (A/D converters 0 and 1): 5 channels + 5 channels (2 units)
  • The one A/D converter 0 channel and three A/D converter 1 channels are provided with an operational amplifier for input level amplification and a comparator for overvoltage detection.
  • 10-bit resolution A/D converter (A/D converter 2): 4/8 channels

Clock generator:

  • 4 to 8 MHz resonator connectable (external clock input prohibited)
  • Multiplication function by PLL clock synthesizer (fixed to multiplication by eight, fXX = 32 to 64 MHz)
  • CPU clock division function (fXX, fXX/2, fXX/4, fXX/8)

Power-save function: HALT/IDLE/STOP mode
Power-on-clear function
Low-voltage detection function

 

Key Applications:

[Consumer equipment] inverter air conditioner
[Industrial equipment] motor control, general-purpose inverter etc.

 

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