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Note that documents distributed herein may be preliminary versions, even if not labeled as such.

Documentation List

CB-40
  • Design Manual
  • Block Library
  • OPENCAD

CB-55
  • Design Manual
  • Block Library
  • OPENCAD

CB-90
  • Design Manual
  • Block Library
  • Data Sheet
  • OPENCAD

CB-12
  • Design Manual
  • Block Library
  • Memory Macro
  • Analog Macro Common
  • Analog Macro
  • OPENCAD

CB-40

Document Name Japanese English
Design Manual L Type Product Data R05UH0009JJ0500_ASICDMCB R05UH0009EJ0500_ASICDMCB
LD Type Product Data R05UH0010JJ0400_ASICDMCB R05UH0010EJ0400_ASICDMCB
Circuit Design A20268JJ1V0DM00 A20268EJ1V0DM00
LR Type Product Data R05UH0008JJ0401_ASICDMCB R05UH0008EJ0201_ASICDMCB
LR Type Circuit Design R05UH0012JJ0200_ASICDMCB -
Block Library L Type (WIDE 1.1V) - R05UH0006EJ0600_ASICBLCB
LR Type (1.1±0.1V) - R05UH0007EJ0500_ASICBLCB
LR Type (1.15±0.1V) - R05UH0018EJ0100_ASICBLCB
L/LD/LR Type (Interface Block) - R05UH0017EJ0201_ASICBLCB
Memory Macro L Type R05UH0014JJ0600_ASICDMCB R05UH0014EJ0600_ASICDMCB
LD Type R05UH0015JJ0400_ASICDMCB R05UH0015EJ0400_ASICDMCB
LR Type R05UH0011JJ0301_ASICDMCB R05UH0011EJ0301_ASICDMCB
Static Timing Analyzer Static Timing Analyzer Operation (PrimeTime/TimeCraft) A17664JJ6V0UM00 A17664EJ3V0UM00
LOCV Verification Guideline (PrimeTime/TimeCraft) A20260JJ1V0UM00 -
Formal Verification Formality Interface A19783JJ1V0UM00 -
Conformal-LEC Interface A19832JJ1V0UM00 -
Design For Test Manual TESTBUS Design Guideline A17104JJ1V0UM00 A17104EJ1V0UM00
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CB-55

Document Name Japanese English
Design Manual L Type Product Data R05UH0013JJ0600_ASICDMCB R05UH0013EJ0600_ASICDMCB
L Type Circuit Design A20211JJ1V0DM00 A20211EJ1V0DM00
Block Library L Type (WIDE 1.2V) - A19128EJ4V0BL00
Memory Macro L Type A19481JJ4V0DM00 A19481EJ4V0DM00
Static Timing Analyzer Static Timing Analyzer Operation (PrimeTime/TimeCraft) A17664JJ6V0UM00 A17664EJ3V0UM00
LOCV Verification Guideline (PrimeTime/TimeCraft) A20260JJ1V0UM00 -
Formal Verification Formality Interface A19783JJ1V0UM00 -
Conformal-LEC Interface A19832JJ1V0UM00 -
Design For Test Manual TESTBUS Design Guideline A17104JJ1V0UM00 A17104EJ1V0UM00
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CB-90

Document Name Japanese English
Design Manual M Type Product Data A17900JJ4V0DM00 A17900EJ4V0DM00
M Type Circuit Design A18903JJ1V2DM00 A18903EJ1V2DM00
L Type Product Data A17901JJ3V0DM00 A17901EJ3V0DM00
Block Library M Type (WIDE 1.0V) - A17270EJBV0BL00
M Type (NARROW 1.0V) - A17355EJ6V0BL00
L Type (WIDE 1.2V) - A17474EJ4V0BL00
Memory Macro M Type A19049JJ4V2DM00 A19049EJ4V2DM00
L Type A19050JJ1V0DM00 A19050EJ1V0DM00
Data Sheet A/D Converter Core -
D/A Converter Core -
OPENCAD Wave Editor A14954JJ2V0UM00 A14954EJ2V0UM00
Design Rule Check STADRC A14967JJ5V0UM00 A14967EJ5V0UM00
Design Rule Check GateDRC A16216JJ2V0UM00 A16216EJ2V0UM00
Constraint Description For Signal Integrity A15882JJ2V0UM00 A15882EJ2V0UM00
Utility A17140JJ2V0UM00 A17140EJ2V0UM00
OPC_VSHELL A17226JJ1V0UM00 A17226EJ1V0UM00
Logic Simulation Simulator (VCS, NC-Verilog, Verilog-XL, ModelSim, V.sim) A16885JJ5V0UM00 A16885EJ4V0UM00
Static Timing Analyzer PrimeTime Interface A14961JJ2V0UM00 A14961EJ2V0UM00
Static Timing Analyzer Operation (Tiara) A15858JJBV0UM00 A15858EJ1V0UM00
Static Timing Analyzer Operation (PrimeTime/TimeCraft) A17664JJ6V0UM00 A17664EJ3V0UM00
LOCV Verification Guideline (PrimeTime/TimeCraft) A20260JJ1V0UM00 -
Static Timing Analyzer Tiara A16210JJ4V0UM00 A16210EJ1V0UM00
Static Timing Analyzer OPC_Tiara A18171JJ1V0UM00 -
Logic Synthesis Design Compiler Interface A17319JJ4V0UM00 A17319EJ2V0UM00
Formal Verification Formality Interface A14968JJ4V0UM00 A14968EJ4V0UM00
Conformal-LEC Interface A16234JJ4V0UM00 A16234EJ4V0UM00
Design For Test TESTACT Operation Manual Circuit Design
(for L Type)		 A17891JJ3V0UM00 -
Manual TESTBUS Design Guideline A17104JJ1V0UM00 A17104EJ1V0UM00
TESTACT Operation Manual A17464JJ4V0UM00 A17464EJ4V0UM00
Tester Interface Test Vector A14966JJ7V0UM00 A14966EJ7V0UM00
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CB-12

Document Name Japanese English
Design Manual L/M Type Product Data A14937JJ6V0DM00 A14937EJ6V0DM00
L/M Type Circuit Design A15135JJ5V1DM00 A15135EJ5V1DM00
Block Library L/M Type (CMOS 1.5V) - A15353EJ5V0BL00
L/M Type (TTL 1.5V) - A15354EJ3V0BL00
Memory Macro L Type A16458JJ2V0DM00 A16458EJ2V0DM00
M Type A16730JJ3V0DM00 A16730EJ3V0DM00
Analog Macro Common Cell-Based IC with PLL A15508JJ5V0DM00 A15508EJ5V0DM00
Cell-Based IC with DAC Circuit Design A15698JJ3V0DM00 A15698EJ3V0DM00
Cell-Based IC with ADC Circuit Design A16347JJ3V0DM00 A16347EJ3V0DM00
OPENCAD Wave Editor A14954JJ2V0UM00 A14954EJ2V0UM00
Design Rule Check STADRC A14967JJ5V0UM00 A14967EJ5V0UM00
Design Rule Check GateDRC A16216JJ2V0UM00 A16216EJ2V0UM00
Constraint Description For Signal Integrity A15882JJ2V0UM00 A15882EJ2V0UM00
Utility A17140JJ2V0UM00 A17140EJ2V0UM00
OPC_VSHELL A17226JJ1V0UM00 A17226EJ1V0UM00
Logic Simulation Simulator (VCS, NC-Verilog, Verilog-XL, ModelSim, V.sim) A16885JJ5V0UM00 A16885EJ4V0UM00
Static Timing Analyzer PrimeTime Interface A14961JJ2V0UM00 A14961EJ2V0UM00
Static Timing Analyzer Operation (Tiara) A15858JJBV0UM00 A15858EJ1V0UM00
Static Timing Analyzer Operation (PrimeTime/TimeCraft) A17664JJ6V0UM00 A17664EJ3V0UM00
LOCV Verification Guideline (PrimeTime/TimeCraft) A20260JJ1V0UM00 -
Static Timing Analyzer Tiara A16210JJ4V0UM00 A16210EJ1V0UM00
Static Timing Analyzer OPC_Tiara A18171JJ1V0UM00 -
Schematic Editor Vdraw A14953JJ2V0UM00 A14953EJ2V0UM00
Logic Synthesis Design Compiler Interface A17319JJ4V0UM00 A17319EJ2V0UM00
Formal Verification Formality Interface A14968JJ4V0UM00 A14968EJ4V0UM00
Conformal-LEC Interface A16234JJ4V0UM00 A16234EJ4V0UM00
Design For Test RobustSCAN A16728JJ4V0UM00 A16728EJ4V0UM00
TESTACT Operation Manual Circuit Design A17891JJ3V0UM00 -
Manual TESTBUS Design Guideline A17104JJ1V0UM00 A17104EJ1V0UM00
TESTACT Operation Manual A17464JJ4V0UM00 A17464EJ4V0UM00
Tester Interface Test Vector A14966JJ7V0UM00 A14966EJ7V0UM00
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