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Speed up your system! Accelerate using a C programmable LSI!

In order to support the advanced and complex processing that is increasingly demanded of LSIs, Renesas Electronics is breaking free from HDL-based design flows to offer programmable LSI solutions.

STP engine (IP core)

STP engine (IP core)

Greatly accelerate performance by using reconfigurable processing for applications for which CPU power is insufficient. Unused circuits are folded away so that a large circuit can be mounted on a limited chip area.

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Immediate effectiveness! System development using LSIs for specific applications (ASSP)

Immediate effectiveness! System development using LSIs for specific applications (ASSP)

Decided on an application field, but having trouble deciding on the system? This is where a programmable LSI comes in handy.
XBridge (cross-bridge) has a proven track record with applications such as broadcasting equipment. Our XBridge partners are also ready to help with application development.

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Proven track record

Proven track record

Our programmable LSIs are used in a broad range of products, from professional video equipment to digital cameras.

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Site Updates

  • Released English site (Feburary, 2012)
  • NEC Electronics Releases SoC Optimized for Stream Processing (November 19, 2008)

International conference

  • Takao Toi, Toru Awashima, Masato Motomura, Hideharu Amano, "Time and Space-multiplexed Compilation Challenges for Dynamically Reconfigurable Processors", IEEE MWSCAS 2011 (Invited Talk), Aug. 2011.
  • Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano, "Wire Congestion Aware Synthesis for a Dynamically Reconfigurable Processor", IEEE FPT 2010, pp.300-303, Dec. 2010.
  • Masato Motomura: "STP Engine, a C-based Programmable HW Core featuring Massively Parallel and Reconfigurable PE Array: Its Architecture, Tool, and System Implications", Proceeding of Cool Chips XII, pp.395-408, Apr. 2009.
  • Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi, Li Jing, "High-level Synthesis Challenges and Solutions for a Dynamically Reconfigurable Processor", IEEE/ACM ICCAD 2006, pp.702-708, Nov. 2006.
  • Masato Motomura: "A Dynamically Reconfigurable Processor Architecture", Microprocessor Forum, Oct. 2002.

Papers

  • Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, and Hideharu Amano, "Iterative Synthesis Methods Estimating Programmable Wire Congestion in a Dynamically Reconfigurable Processor", IEICE Transaction on Fundamentals, Vol. E-94-A, No. 12, pp.2619-2627, Dec. 2011.
  • Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi, "High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable Processor", IPSJ Trans. on System LSI Design Methodology, Vol. 3, pp.91-104 , Feb. 2010.

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